Time-interleaving is used almost universally in radio frequency (RF) sampling analog-to-digital converters (ADCs). Time-interleaved ADCs instantiate several ADC channels in parallel with sampling points spread evenly across the channels. The main advantage is that the overall ADC sampling rate is N times higher than using a single channel (where N is the number of channels).
The limitation of time-interleaving is that in the presence of unavoidable mismatch, the output spectrum is corrupted. The offset, gain, and timing mismatch errors can be calibrated to reduce them to acceptable levels. However, flicker noise in the ADC channels is up-converted and appears around the offset spurs. This flicker noise cannot be calibrated and is an increasing problem in deeply-scaled complementary metal oxide semiconductor (CMOS) devices.
Chopping is a technique to frequency-translate circuit non-idealities with the goal of minimizing their impact on circuit performance. When applied to a time-interleaved ADC, chopping can spread out offset errors or flicker noise across frequency, preventing serious corruption of the spectrum near the ADC offset frequencies. This chopping can be added to any ADC architecture by adding a second set of sampling switches that sample the signal with opposite polarity to the original set of sampling switches. By selectively acquiring the input signal using one or the other set of switches and inverting the output signal when appropriate, the chopping operation is achieved. When chopping is not required, the additional switches can simply be disabled and do not adversely affect performance in any way. However, one drawback of this technique is that the newly added switches are subject to sampling time mismatch, which can lead to serious degradation of the converter noise floor.